The present invention relates to a code error corrector, and more particularly, to a device for correcting code errors in data to which error correction codes are added when reproducing the data.
When recording data to a recording medium, an error detection code (EDC) and an error correcting code are usually added to the data so that the data may be reproduced with high reliability.
For example, in a DVD recorder that uses a digital versatile disk (DVD) as a recording medium, the data subject to recording is recorded in a plurality of DVD data sectors. Each DVD data sector has a logical layout, which is shown in FIG. 1.
The data subject to recording is first divided into units of 2,048 bytes. The data in each 2,048 byte data unit is referred to as main data. A header configured by 12 bytes of data is added to the head of each data unit, and an EDC configured by 4 bytes of data is added to the end of each data unit. The header is configured from 4 bytes of a sector number (ID), 2 bytes of an error detection parity (IED) for the ID, and 6 bytes of reserved data (CPM) such as copy protection information. The EDC serves as a detection parity for the section configured by the main data and the header. Accordingly, a single data sector is configured by 2,064 bytes of data, which includes the main data, the header, and the EDC. Further, the data sector includes twelve rows with each row having 172 bytes. To scramble the main data in the data sector, a pseudo-random noise (PN) sequence adding is performed.
Referring to FIG. 2, 16 rows of an outer code parity (PO) and 10 columns of an inner code parity (PI) are added to 16 successive data sectors 0 to 15. The 16 successive data sectors 0 to 15 consist of 192 rows with each row consisting of 172 bytes. The ECC block has 208 rows with each row having 182 bytes (182 bytes×208 rows). The 208 rows of data, with each row consisting of 182 bytes, in which the PO and PI have been added is referred to as an error check and correction (ECC) block. The ECC block is the unit in which error correction and error detection are performed.
The PI added to each row is an error correction code that is based on the 172 bytes of data included in the row. Further, the PO added to each column is generated based on the 192 bytes of data included in the column.
Referring to FIG. 3, the 16 rows of the PO are each sequentially moved to a location following one of the 16 data sectors, to which the PI has been added. Thus, for each data sector, 10 bytes of the PI are added to each row and the PO is added in a 13th line. This generates a recording sector configured by 13 rows, with each row consisting of 182 bytes. In this manner, the ECC block, the rows of which are rearranged, configures 16 recording sectors. Hereafter, the ECC block of which rows are rearranged (FIG. 3) will hereinafter be simply referred to as a block.
The block undergoes 8–16 modulation, which is performed in DVDs, to generate recording data. The recording data is converted to serial data and then written to a DVD, which serves as the recording medium.
When reading the recording data from the DVD, dust or scratches on the surface of the DVD may affect the reading. In such a case, the read recording data may not be the same as the actually recorded data. In other words, a code error may be included in the read recording data. Thus, error correction and error detection are performed on the recording data with an error correction code, such as the PI and the PO, and the EDC.
The error correction and error detection are each performed by reading data from a memory and processing the data and then rewriting the processed result to the memory. Such series of processes are referred to as error check and correction (ECC), and the group of circuits performing ECC is referred to as an error check and correction unit.
FIG. 4 is a block diagram of a conventional code error corrector 100. The code error corrector 100 includes an ECC unit 133, which performs ECC.
Referring to FIG. 4, a pickup 111 detects a signal from a DVD. An RF amplifier 112 amplifies the signal and provides the amplified signal to the code error corrector 100. In accordance with the signal provided from the RF amplifier 112, a read channel circuit 113 generates a read channel clock signal, which has a predetermined frequency, and samples an input signal in accordance with the read channel clock signal to generate data. A synchronization detection circuit 114 detects a synchronization signal that corresponds to the block of the sampled signal and provides the synchronization signal to a control circuit 131. A demodulation circuit 115 demodulates the generated data to restore the original data that was subject to recording (the data prior to modulation) and provides the restored original data to the buffering circuit 116. The control circuit 131 provides the buffering circuit 116 with a write command in synchronism with the synchronization signal from the synchronization detection circuit 114. The buffering circuit 116 writes the data received from the demodulation circuit 115 to a dynamic random access memory (DRAM) 118, which is an external memory, via a memory access circuit 117.
In this manner, the recording data read from the DVD is sequentially stored in a ring buffer of the DRAM 118 in units of blocks. The ECC unit 133 performs error correction and error detection on the recording data stored in the DRAM 118 in synchronism with the synchronization signal.
The ECC unit 133 includes an error detection circuit 122, which performs error detection, and a correction circuit 130, which performs error correction. The correction circuit 130 includes a PI correction circuit 120, which performs error correction on a PI, and a PO correction circuit 126, which performs error correction on a PO.
FIG. 5 is a timing chart illustrating the operation timing of the buffering and the ECC, which are performed in synchronism with the synchronization signal detected by the synchronization detection circuit 114. The cycle in which the synchronization signal goes high corresponds to one synchronization cycle.
In synchronization cycle T(0), the buffering circuit 116 first buffers block 0. The control circuit 131 of FIG. 4 sends an interrupt request IRQ to an external circuit (not shown) in synchronism with the synchronization signal of the control circuit 131. The external circuit reads an identification number BID, which identifies the block subject to buffering, from the control circuit 131.
In the next synchronization cycle T(1), the buffering circuit 116 buffers block 1 (refer to FIG. 6), which follows block 0, and the ECC unit 133 performs ECC on block 0. When the next synchronization cycle T(2) starts, block 0, which has undergone the ECC, is read from the DRAM 118 in response to the interrupt request IRQ, which is issued by the control circuit 131.
In the same manner, the buffered block undergoes ECC in the next synchronization cycle. The block that has undergone the ECC is read from the DRAM 118 in response to the interrupt request IRQ of the next synchronization cycle. The identification number BID may be the ID of all of the 16 data sectors included in the corresponding block or the ID of the head data sector in the corresponding block.
To perform ECC and buffering in parallel, the control circuit 131 manages pointer information, which indicates the block that is subject to ECC or buffering. FIG. 6 illustrates a block stored in the DRAM 118 that should undergo buffering and ECC. Pointer information BUF_PTR indicates block 1, and pointer information ECC_PTR indicates block 0. In other words, FIG. 6 illustrates the state of the ring buffer at time 1 of FIG. 5. As can be understood from the timing chart of FIG. 5, the pointer information ECC_PTR always indicates the block that is just one block ahead of the block indicated by pointer information BUF_PTR.
FIG. 7 and FIG. 8 are flowcharts respectively illustrating the buffering and ECC in the prior art.
The buffering will first be discussed with reference to FIG. 7.
In response to a buffering initiation command from an external circuit, the control circuit 131 starts buffering. In step S161, the control circuit 131 initializes the pointer information BUF_PTR. In step S162, the control circuit 131 waits until detecting a block synchronization signal. When provided with the block synchronization signal from the synchronization detection circuit 114, in step S163, the control circuit 131 checks whether a buffering command is being issued. If the buffering command is not being issued, the control circuit 131 ends the buffering. If the buffering command is being issued, in step S164, the control circuit 131 instructs the buffering circuit 116 to buffer the block indicated by the pointer information BUF_PTR. After buffering the block, in step S165, the control circuit 131 increments the pointer information BUF_PTR by one block. Then, the control circuit 131 returns to a state in which it waits for the block synchronization signal (step S162).
The ECC will now be discussed with reference to FIG. 8.
In response to an ECC initiation command from an external circuit, in step S171, the control circuit 131 initializes the pointer information ECC_PTR. In step S172, the control circuit 131 waits until detecting the block synchronization signal. When receiving the block synchronization signal from the synchronization detection circuit 114, in step S173, the control circuit 131 checks whether an ECC command is being issued. If the ECC command is not being issued, the control circuit 131 ends the ECC. If the ECC command is being issued, the control circuit 131 activates the ECC unit 133.
The ECC unit 133 performs the steps subsequent to step S174. The data scrambled as described with FIGS. 1 to 3 is the subject of the error correction.
To increase the reliability of the reproduced data, the ECC unit 133 repetitively performs the series of processing on the PI and the PO a predetermined number of times, for example, two times. In such a case, the ECC unit 133 switches a switching circuit 127, which is connected to a FIFO 121, to select route R3, which bypasses a descrambling circuit 125. After switching the switching circuit 127, the ECC unit 133 starts performing ECC.
The PI correction circuit 120, which performs error correction of a PI, reads data SCD1, which is subject to the PI error correction (PI correction) for the first time, from the recording data stored in the DRAM 118 via an FIFO 119 and stores the data SCD1 in a data storage section 120a. In this state, the amount of the data SCD1 stored in the data storage section 120a is 182 bytes (172 bytes of main data and 10 bytes of the PI), which corresponds to one row of the recording sector illustrated in FIG. 3. Then, a syndrome calculation circuit 120b of the PI correction circuit 120 retrieves the data SCD1 from the data storage section 120a, and the data storage section 120a provides the data SCD1 to a syndrome calculation circuit 126b of the PO correction circuit 126, which performs error correction of a PO. In this state, instead of providing the syndrome calculation circuit 126b with the data SCD1, the data storage section 120a may provide the syndrome calculation circuit 126b with data SCD1(I) that has undergone PI correction (described later).
The syndrome calculation circuit 120b calculates a PI syndrome V(I) and provides the syndrome V(I) to a PI correction circuit 120c of the PI correction circuit 120. Based on the syndrome V(I), the PI correction circuit 120c correctly rewrites the erroneous part of the data stored in the data storage section 120a to perform PI correction. Then, the PI correction circuit 120c provides the PI corrected data SCD1(I) to the DRAM 118 via the FIFO 121.
At the same time, the syndrome calculation circuit 126b of the PO correction circuit 126 calculates a syndrome V(0) of each column of the PO for the row of data SCD1 from the data storage section 120a and provides the syndromes V(0) to a PO syndrome storage section 126a. In this state, the syndromes V(0) for 182 columns are stored in the PO syndrome storage section 126a. 
Such processing is repetitively performed 16 times for the 13-row recording sectors to complete the PI correction of one block of data. In this state, the PO syndrome storage section 126a stores the PO syndromes V′(0) for 182 columns×16. A PO correction circuit 126c retrieves the syndromes V′(0) from the PO syndrome storage section 126a, retrieves the PI corrected data from the DRAM 118 via an FIFO 123, and completes the PO error correction of the recording sector (steps S174 and S175). As a result, the error corrected data SCD1(0) for the first PI and PO are stored via the FIFO 123 in the DRAM 118.
When the first PI and PO corrections are completed, the PI and PO corrections are performed for a second time. The route configured by the switching circuit 127 is switched to route R4, which is used to perform descrambling. After the switching to route R4, the data SCD1(0) of the first PI and PO corrections are stored in the data storage section 120a of the PI correction circuit 120 via the FIFO 119. Then, the PI correction circuit 120 performs PI correction on the data stored in the data storage section 120a and calculates the PO syndrome V(0). Then, the PI correction circuit 120 provides the descrambling circuit 125 with data SCD2(I) that was PI corrected for the second time. The descrambling circuit 125 descrambles the data SCD2(I) and stores the descrambled data DSD2(I) in the DRAM 118 via the FIFO 121. Further, the syndrome calculation circuit 126b calculates the PO syndrome V(0) and stores the calculated PO syndrome V(0) in the PO syndrome storage section 126a. 
Such processing is repeated for one block to perform PI correction for the second time and store the final syndromes V′(0) for the one block in the PO syndrome storage section 126a. The PO correction circuit 126c retrieves the data DSD2(I) that has been PI corrected and descrambled for the second time from the DRAM 118 via an FIFO 123 and performs PO correction. Data DSD2 (0) that has undergone PO correction for the second time is stored in the DRAM 118 via the FIFO 123 (steps S176 and S177). The ECC is described in, for example, Japanese Laid-Open Patent Publication No. 2001-237715. Then, the error detection circuit 122 performs error detection on the data DSD2(0) that has undergone error correction two times for the PI and two times for the PO (step S178). In the error detection, the error detection circuit 122 compares the accumulatively added value of the main data for each recording sector and the EDC included in the recording sector. The error detection circuit 122 determines whether the accumulatively added value matches the EDC in every recording sector of the block and writes the results to the control circuit 131.
Finally, in step S179, the control circuit 131 increments pointer information ECC_PTR, completes the ECC of the data of the block, and returns to a state in which it waits for the next block synchronization signal.
In this manner, the data of the block that has completed ECC is ultimately stored in the DRAM 118 in a descrambled state. In step S174, data is re-written to the DRAM 118 without being descrambled so that scrambled data is read when performing error correction again later on.
FIG. 9 is a timing chart illustrating the conventional buffering and the ECC. In synchronization cycle T (N+1), the buffering circuit buffers block (N+1). Further, the ECC unit 133 performs error correction two times on the PI and on the PO for block N.
In the following synchronization cycle T(N+2), the buffering circuit 116 buffers block (N+2). Further, the ECC unit 133 performs error correction two times on the PI and on the PO for block (N+1).
In this manner, the data of the block buffered by the buffering circuit 116 always undergoes error correction of the PI for two times and the PO for two times in the next synchronization cycle before being stored in the DRAM 118.
In a prior art DVD reproduction device, the DRAM 118 is accessed not only by the code error corrector 100 but also by other circuits, such as microcomputers (not shown). Accordingly, as the frequency of accesses to the DRAM 118 increases, the access waiting time becomes longer. The long access waiting time makes it difficult to increase the speed for reproducing the data recorded to the DVD.